general description the max3981 quad equalizer provides compensationfor transmission medium losses for four ?anes?of digi- tal nrz data at a data rate of 3.125gbps in one package. it is tailor-made for 10gigabit ethernet appli- cations that require attenuation of noise and jitter that occur in communicating with chassis-to-chassis inter- connect. in support of ieee-802.3ae for the xaui inter- face, the max3981 adaptively allows xaui lanes to reach 10m (33ft) with inexpensive twin-axial cable for extended backplane applications. the equalizer has 100 differential cml data inputs and outputs.the max3981 is available in a 44-pin exposed-pad qfn package. the max3981 consumes only 700mw at 3.3v or 175mw per channel. applications ieee?02.3ae xaui interface (3.125gbps)infiniband sm (2.5gbps) features ? four differential digital data lanes at 3.125gbps ? span 10m (33ft) of twin-axial cable ? receiver equalization reduces intersymbol interference (isi) ? low power, 175mw per channel ? standby mode power-down state ? single 3.3v supply ? signal detect max3981 3.125gbps xaui quad cable equalizer ___________________________________________________ _____________ maxim integrated products 1 ordering information line card pmd mac rx rx tx tx rx rx tx tx 10gbe 4 4 4 4 4 4 4 x 3.125gbps switch card max3981 out in 3.3v supply max3981 in out 3.3v supply 10m (33ft)100 twin-ax cable switch rx tx typical operating circuit 19-2178; rev 2; 12/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration appears at end of data sheet. * ep = exposed pad. par emp range pin-package max3981ugh 0c to +85c 44 qfn-ep* infiniband is a trademark and service mark of the infiniband trade association. downloaded from: http:///
max3981 3.125gbps xaui quad cable equalizer 2 __________________________________________________ _____________________________________ absolute maximum ratings electrical characteristics (v cc = +3.0v to +3.6v, input data rate = 3.125gbps, t a = 0? to +85?. typical values are at v cc = +3.3v and t a = +25?, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage, v cc ..............................................-0.5v to +4.0v voltage at sdet .........................................-0.5v to (v cc + 0.5v) voltage at in_ ...........................................-0.5v to (v cc + 0.5v) current out of out_ .......................................-25ma to +25ma continuous power dissipation (t a = +85?) 44-pin qfn-ep (derate 26.3mw/? above +85?)....2105mw operating ambient temperature range ................0? to +85? storage temperature range .............................-55? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units en = ttl low 0.25 supply power en = ttl high 0.7 0.9 w 10hz < f < 100hz 100 100hz < f < 1mhz 40 supply noise tolerance 1mhz < f < 2.5ghz 10 mvp-p signal detect assert input signal level to assert sdet (note 1) 100 mvp-p signal detect deassert input signal level to deassert sdet (note 1) 30 mvp-p signal detect delay delay time in detecting a change inpresence of a signal (note 4) 10 s latency from input to output 0.32 ns cml receiver input input voltage swing xaui transmitter output measureddifferentially at point a, figure 1, using k28.5 pattern (note 4) 200 800 mvp-p return loss 100mhz to 2.5ghz 12 db input resistance differential 80 100 120 equalization total jitter (notes 2, 4) 0.3 residual jitter deterministic jitter (note 4) 0.2 uip-p random jitter (note 2) 1.5 ps rms cml transmitter output (into 100 1 ) output voltage swing differential swing 550 850 mvp-p common-mode voltage v cc - 0.3 v transition time t f , t r 20% to 80% (notes 3, 4) 60 130 ps differential skew difference in 50% crossing between out_+and out_- (note 4) 12 ps output resistance single ended 40 50 60 downloaded from: http:///
max3981 3.125gbps xaui quad cable equalizer ___________________________________________________ ____________________________________ 3 electrical characteristics (continued) (v cc = +3.0v to +3.6v, input data rate = 3.125gbps, t a = 0? to +85?. typical values are at v cc = +3.3v and t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units ttl control pins input high voltage 2.0 v input low voltage 0.8 v input high current 250 a input low current 500 a output high voltage internal 10k pullup 2.4 v output low voltage internal 10k pullup 0.4 v note 1: k28.7 pattern is applied differentially at point a as shown in figure 1. note 2: total jitter does not include the signal source jitter. total jitter (tj) = ( 14.1 ? rj + dj) where rj is random rms jitter and dj is maximum deterministic jitter. signal source is a k28.5 pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and k28.7 (0011111000) or equivalent for the random jitter test. residual jitter is that which remains after equalizing media-induced losses of the environment of figure 1 or its equivalent. the deterministic jitter at point b must be from media- induced loss and not from clock source modulation. jitter is measured at 0v at point c of figure 1. note 3: using k28.7 (0011111000) pattern. note 4: ac specifications are guaranteed by design and characterization. out in smaconnector sma connector a b c signal source madison #14487, 100 shielded twisted pair 2" 2" 10 feet fr4 cable fr4 max3981 figure 1. test conditions referenced in the electrical characteristics table downloaded from: http:///
max3981 3.125gbps xaui quad cable equalizer 4 __________________________________________________ _____________________________________ typical operating characteristics (v cc = +3.3v, 3.125gbps, 500mvp-p cable input with 2 7 - 1 prbs, t a = +25?, unless otherwise noted. note: twin-axial cable used was tensolite, z-skew, 100 , 28awg. shielded twisted pair used was madison 100 , 30awg, spec #14887.) equalizer input eye diagram after 10m (33ft) of twin-axial cable max3981 toc01 50ps/div 100mv/ div equalizer output eye diagram after 10m (33ft) of twin-axial cable max3981 toc02 50ps/div 100mv/ div 7050 130110 90 170 190150 210 03 0 4 0 10 20 50 60 70 80 equalizer operating current vs. temperature max3981 toc03 temperature ( c) current (ma) normal operation (en = ttl high) standby power (en = ttl low) equalizer input eye diagram after 5m (16ft) of shielded twisted pair max3981 toc04 50ps/div 60mv/ div equalizer output eye diagram after 5m (16ft) of shielded twisted pair max3981 toc05 50ps/div 100mv/ div -50 -30-40 -10-20 0 10 50 input return gain (s11, differential, input signal = -60dbm, device powered off) max3981 toc06 frequency (mhz) gain (db) 2050 1050 3050 4050 5050 0 3020 10 40 50 60 04 3 12 5678910 equalizer deterministic jitter vs. cable length (k28.5 pattern, 3.125gbps) max3981 toc07 length (m) jitter (ps) shielded twisted pair (madison) twin-axial (tensolite) 0 3020 10 40 50 60 04 3 12 5678910 equalizer deterministic jitter vs. cable length (k28.5 pattern, 2.5gbps) max3981 toc08 length (m) jitter (ps) shielded twisted pair (madison) twin-axial (tensolite) 200 250 300 350 400 450 500 02 0 10 30 40 50 60 70 80 90 equalizer latency vs. temperature max3981 toc09 temperature ( c) delay (ps) downloaded from: http:///
max3981 3.125gbps xaui quad cable equalizer ___________________________________________________ ____________________________________ 5 pin description pin name function 1, 5, 9, 13, 23, 27, 31, 35 v cc +3.3v supply voltage 4, 8, 12, 16, 26, 30, 34, 38 gnd supply ground 2 in1+ positive equalizer input channel 1, cml 3 in1- negative equalizer input channel 1, cml 6 in2+ positive equalizer input channel 2, cml 7 in2- negative equalizer input channel 2, cml 10 in3+ positive equalizer input channel 3, cml 11 in3- negative equalizer input channel 3, cml 14 in4+ positive equalizer input channel 4, cml 15 in4- negative equalizer input channel 4, cml 17C22, 39C42 n.c. no connection. leave unconnected. 24 out4- negative equalizer output channel 4, cml 25 out4+ positive equalizer output channel 4, cml 28 out3- negative equalizer output channel 3, cml 29 out3+ positive equalizer output channel 3, cml 32 out2- negative equalizer output channel 2, cml 33 out2+ positive equalizer output channel 2, cml 36 out1- negative equalizer output channel 1, cml 37 out1+ positive equalizer output channel 1, cml 43 en enable equalizer input. a ttl high selects normal operation. a ttl low sel ects low-power standby mode. 44 sdet signal detect output for channel 1. produces a ttl high out put when a signal is detected. ep exposed pad. the exposed pad must be soldered to the circuit board ground plane for proper thermal and electrical performance. downloaded from: http:///
max3981 detailed description receiver and transmitter the adaptive equalizer accepts four lanes of3.125gbps cml digital data signals and compensates each received signal for dielectric and skin losses. a limiting amp shapes the output of the equalizer and the output driver transmits the regenerated xaui lanes as cml signals. the source impedance and termination impedance are 100 differential. general theory of operation internally, the max3981 is comprised of signal-detectcircuitry, four matched equalizers, and one equalizer control loop. the four equalizers are made up of a mas- ter equalizer and three slave equalizers. the adaptive control is generated from only channel 1. it is assumed that all channels have the same characterization in fre- quency content, coding, and transmission length. the master equalizer consists of the following func- tions: signal detect, adaptive equalizer, equalizer con- trol, limiting and output drivers. the signal detect indicates input signal power. when the input signal level is sufficiently high, the sdet output is asserted. this does not directly control the operation of the part. the equalizer core reduces intersymbol interference (isi), compensating for frequency-dependent, media- induced loss. the equalization control detects the spectral contents of the input signal and provides a control voltage to the equalizer core, adapting it to dif- ferent media. the equalizer operation is optimized forshort-run dc-balanced transmission codes such as 8b/10b codes. cml input and output buffers the input and output buffers are implemented usingcurrent -mode logic (cml). equivalent circuits are shown in figures 2 and 3. for details on interfacing with cml,see maxim application note hfan-1.0, interfacing between cml, pecl, and lvds . the common-mode voltages of the input and output are above 2.5v. ac-coupling capacitors are required when interfacing this part. values of 0.10? or greater are recommended. media equalization equalization at the input port compensates for the high-frequency loss encountered with twin-axial cable or shielded twisted pair. this part is optimized for 10ft (3m) and 3.125gbps; however, the part will reduce isi for signals spanning longer distances and functions for data rates from 2gbps to 4gbps providing that short- length balanced codes, such as 8b/10b, are used. applications information standby mode the standby state allows reduced-power operation.the ttl input, en, must be set to ttl high for normal operation. a ttl low at en forces the equalizer into the standby state. the signal en does not affect the opera- 3.125gbps xaui quad cable equalizer 6 __________________________________________________ _____________________________________ in1+ in1- equalizer limiting amp 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 out1+ out1- 2 3 4 2 3 4 en power management sdet function isindependent of en sdet ttl cml signal detect ip1, in1 only max3981 functional diagram downloaded from: http:///
tion of the signal detect (sdet) function. for constantoperation, connect the en signal directly to v cc . signal detect with standby mode signal activity is detected on channel 1 only (in1?. when the peak-to-peak differential voltage at in1 is less than 30mvp-p, the ttl output sdet goes low. when the peak-to-peak differential voltage becomes greater than 100mvp-p, sdet is asserted high. sdet can be used to automatically force the equalizer into standby mode by connecting sdet directly to the en input. when not used, sdet should not be connected. the signal-detect function continues to operate while the part is in standby mode. while connected to the en pin, the signal detect can ?ake up?the part and resume normal operation. layout considerations circuit board layout and design can significantly affectthe max3981 performance. use good high-frequency design techniques, including minimizing ground induc- tances and vias and using controlled-impedance trans- mission lines for the high-frequency data signals. signals should be routed differentially to reduce emi susceptibility and crosstalk. power-supply decoupling capacitors should be placed as close as possible to the v cc pins. max3981 3.125gbps xaui quad cable equalizer ___________________________________________________ ____________________________________ 7 v cc 1.2k 50 50 200 a in+ in- esd structures figure 2. cml input buffer 50 50 v cc q1 q2 out+out- data esd structures figure 3. cml output buffer downloaded from: http:///
max3981 3.125gbps xaui quad cable equalizer 8 __________________________________________________ _____________________________________ pin configuration out2+ out2-gnd out3+ gnd out4+out4- v cc out3-v cc v cc in1- gnd v cc in2+ in2- gnd v cc in3+ in3- in1+ v cc 12 3 4 5 6 7 8 9 1011 1213 14 15 16 17 18 19 20 21 22 4443 42 41 40 39 38 37 36 35 34 3332 31 30 29 28 27 26 25 24 23 gnd n.c.n.c. n.c. n.c. n.c. in4- in4+ v cc gnd enn.c. n.c. n.c. n.c. gnd out1+ out1- v cc gnd sdet max3981 n.c. top view *ep * note: exposed pad must be soldered to supply ground. qfn-ep package information for the latest package outline information and land patterns, goto www.maxim-ic.com/packages . package type package code document no. 44 qfn-ep g4477-1 21-0092 downloaded from: http:///
max3981 3.125gbps xaui quad cable equalizer maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 _____________________ 9 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 12/01 initial release. added the package code to the ordering information table. 1 1 5/03 updated the 21-0092 package drawing in the package information section. 8, 9 2 12/08 changed the absolute maimum ratings of sdet, in_ from +5.0v to (v cc to 0.5v) to C5.0v to (v cc to 0.5v). 2 downloaded from: http:///
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